module insn_mem_top(clk,rst,insn_Address,insn);
  
  input clk,rst;
  input [31:0] insn_Address;
  
  output [31:0] insn;
  
  reg [31:0] insn_RAM[63:0];
  reg [31:0] insn;
//  wire [31:0] insn_Address_t;
  
 // assign insn_Address_t=insn_Address;
  
  //instruction
  parameter inst_0 = 32'b00110101000010000000000000000001;
  parameter inst_1 = 32'b00110101001010010000000000000100;
  parameter inst_2 = 32'b00110101010010100000000000010000;
  parameter inst_3 = 32'b00010010000010100000000000100000;
  parameter inst_4 = 32'b00000010000100000100000000100000;
  parameter inst_5 = 32'b10101101011100000000000000000100;
  parameter inst_6 = 32'b00000001011010110100100000100000;
  parameter inst_7 = 32'b00001000000000000000000000001100;
  parameter inst_8 = 32'b00000010000100000000000000100100;
  parameter inst_9 = 32'b00010010000010100000000000110100;
  parameter inst_10 = 32'b00000010000100000100000000100000;
  parameter inst_11 = 32'b00000010001100011000000000100000;
  parameter inst_12 = 32'b00001000000000000000000000100100;
  parameter inst_13 = 32'b10101101011100010000000000000100;

  always @(*)
  begin
    if(~rst)
      begin
       insn_RAM[0] <= inst_0;
       insn_RAM[4] <= inst_1;
       insn_RAM[8] <= inst_2;
       insn_RAM[12] <= inst_3;
       insn_RAM[16] <= inst_4;
       insn_RAM[20] <= inst_5;
       insn_RAM[24] <= inst_6;
       insn_RAM[28] <= inst_7;
       insn_RAM[32] <= inst_8;
       insn_RAM[36] <= inst_9;
       insn_RAM[40] <= inst_10;
       insn_RAM[44] <= inst_11;
       insn_RAM[48] <= inst_12;
       insn_RAM[52] <= inst_13;
     end
  end

  // Memory Read
  
  always @(posedge clk)
  
  begin
    
    if(1) insn <= insn_RAM[insn_Address];
  
  end 
  
endmodule
